A Study On Input Output Techniques Information Technology Essay
|✅ Paper Type: Free Essay||✅ Subject: Information Technology|
|✅ Wordcount: 2345 words||✅ Published: 1st Jan 2015|
Users interact with the computer system through Input and Output (I/O) devices such as keyboard, mouse, monitor and so on. I/O devices are also called peripherals. I/O devices are used to exchange information between user and CPU. An I/O organisation includes two major components namely I/O devices, I/O module. In addition it uses different techniques to exchange information namely programmed I/O, Interrupt I/O and Direct Memory Access (DMA).
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I/O devices are available with different of working function. Figure 4.1 shows General block diagram computer system organisation that shows CPU, I/O module and memory is connected to each other via system bus. I/O devices are connected to I/O module through interface, which has line connecting to I/O module. Line is used to exchange control signal, status signal and data between the I/O module and the I/O devices.
Figure 4.1: Generic Model of Computer Organisation
System bus includes three lines and types are as follows:
Address Line – Each I/O device is assigned a unique address. To identify the device which sent the request CPU places specific address on the address line.
Control Line – It issues command to perform specific operation such as read or write.
Data Line – The read/write operation or task that is transferred on the data line.
Hardware interface is use to make interaction between I/O devices and system buses. Hardware interface has four components namely address decoder, control circuit, status register and data register.
Address Decoder – It decodes address of the I/O device, when I/O device makes any request to the CPU.
Control Circuit – It exchange control information to the CPU.
Status Register – It contains information about status of the device, related to the operation to be performed. It is connected to the data bus.
Data register – It is connected to the data line, it performs read or write operation based on control signal.
4.2 I/O Module
I/O module is intermediate between I/O devices and CPU. System buses are connected to the one end of I/O module and other end is connected to the number of I/O devices. It used to exchange information between I/O devices and CPU. I/O devices cannot be directly connected to the system buses; they are connected to the system buses through module.
There are several reasons for not connecting I/O devices directly to the system buses and they are as follow:
Varity of I/O devices are available with different operation method. It was not possible to develop operation logic of each I/O devices in the CPU itself.
The I/O devices are much slower than that the CPU. Hence it is not possible to match to match high speed of CPU with speed of I/O devices.
As I/O devices are made with different operation method some of them uses different data formats. It was impractical to integrate each data format in the CPU.
Thus I/O module is used to match speed, operation method and data format between CPU and I/O devices
Functions of I/O Module
The major functions of modules are categorised as follows:
Control and Timing – In some of the I/O operation few resources shared such as CPU and memory because CPU communicates with more than one device at a time. Control and timing function synchronises data flow between I/O devices and internal resources such as memory and CPU.
Processor Communication – I/O module communicates with the CPU and I/O devices. It performs following steps:
Status inquiry of I/O device from I/O module.
I/O module responds back.
If device is ready, CPU gives instruction to I/O module to begin data transfer.
I/O module accepts data from I/O device and transfers it to the CPU.
Device Communication – In addition I/O module communicates with I/O devices.
Features of I/O Module
Data Buffering – As I/O devices are much slower than CPU and memory. In order to maintain speed of data flow between I/O devices and internal resources, I/O module buffers data. Device can access take buffered data any time without holding system bus.
Error Detection – It is built- in feature of I/O module that detects electrical and mechanical errors.
4.3 I/O Module Structure
The I/O module is connects to the rest of computer system through system buses.
Data transferred to and from the module are buffered in one or more data registers. There may be also one or more status registers that provide current status information. A status register may also function as a control register, to accept detailed control information from the processor via a set of control lines. The logic within the module interacts with the processor via a set of control lines. The CPU uses the control lines to issue commands to the I/O module. The module must also be able to recognise and generate address associates with the device it controls. Each I/O module has unique address (Refer to Figure 7.2).
Figure 4.2: General structure of I/O Module
4.4 I/O Technique
It is the technique of communication between memory and I/O devices. I/O techniques are categorised in three types based on how information is transfers between memory and I/O devices that whether it is using CPU interaction or Interrupt interaction.
Types of I/O technique are as follows:
Direct Memory Access (DMA)
4.4.1 Programmed I/O
It involves CPU intervention in communication between CPU and memory. When CPU is executing a program and if encounter an instruction related to I/O operation, CPU executes that instruction by issuing command to I/O module. I/O module will perform the request action and then set the appropriate bits in the I/O status registers (Refer to Figure 4.3). However, this is time consuming process that keeps the CPU busy unnecessary. In this case CPU and memory access the same system bus. The CPU access specific device using two different methods and they are as follows:
Memory mapped I/O – In this technique only single read and write line for memory and I/O module read/write operation. Memory devices and I/O devices are accessed by same instruction. (Refer to Figure 4.3).
Figure 4.3: Memory Mapped I/O
I/O mapped I/O – in this technique memory device and I/O devices are arranged separately. Read and write lines are also separate for read and write operation. (Refer to Figure 4.4).
Figure 4.4: I/O Mapped I/O
Commands are of four types and they are as follows:
Control – It is used to activated the I/O devices and instruct the device about action to be performed.
Test – It used to test various status conditions related to the I/O devices.
Read – It is the command which instruct I/O module to obtain data from I/O device and place it in an internal buffer.
Write – It is the command which instruct ` module to take data from data bus and subsequently transfer it to the I/O device.
Figure 4.5: Flowchart for Programmed I/O
4.4.2 Interrupt ââ‚¬” Driven I/O
The problem with programmed I/O is that CPU has to wait for long time, till instruction gets executed. An alternative is for the CPU to issue an I/O command to a module and then go to do the some other useful work; the I/O module will interrupt the CPU to request service when it is ready to execute the data. (Refer to Figure 4.6). This technique improved performance of the CPU of skipping CPU waiting time till the I/O operation performs.
Figure 4.6: Interrupt Driven I/O
4.4.3 Direct Memory Access (DMA)
DMA uses special I/O CPU that take control of an I/O operation to move large block of data. This technique adds additional module on system bus.
When CPU needs to read or write data, it issues command to the DMA module, by sending following information:
Whether a read and write is requested, using read, or write control line between the CPU and DMA module.
The address of I/O module involved, communicated on the data line.
The starting location is in memory to read from or write to, communicated on the lines and stored by the DMA module in its address registers.
The number of words to be read or written, again communicated via the data lines and stored in the data count register. The CPU then continues with other work.
DMA Data Transfer Modes
There are three typed of data transfer modes and they are as follows:
Block Transfer Mode – In this transfer mode DMA controller takes control of system bus through system bus. It transfers blocks of data. This system is used in very high speed secondary memory and latest microprocessors. While data is transferring CPU does some internal operation that does not require system bus interaction.
Cycle Stealing – In this case instead of transferring entire block of data, it transfers only word by word. DMA forces CPU to pause running operation for a short time. Cycle is stole only when CPU is using some work that does not require system bus.
Interleaved – Interleaved is same as block transfer modem, only difference is it takes control of system bus, when CPU is not using it.
There are two types of configuration and they are as follows: In first type, it allows DMA, I/O and all types of modules to share the same system bus. In the second type, direct path should be established between the DMA and I/O module without any intervention of the system bus.
4.5 Intel 8237A DMA Controller
The Intel 8237A DMA controller interfaces to 8086 CPU family (Refer to Figure ââ‚¬¦.). Configuration of Intel 8237A is as follows:
Four Independent I/O channels.
27 registers, out of these seven are for system wide registers and five for each I/O channel.
Out of five registers, four are 16 bit and one is 6 bits. They are as follows:
6 bit is mode register
DMA based address
DMA current address
DMA operation will flow from following steps and they are as follows:
The peripheral device will request for the service, so DREQ (DMA Request) line will be activated.
The DMA will put high on its HRQ (Hold Request), signaling the CPU through its HOLD pin that it needs to use the buses.
CPU will finish the present bus cycle and respond to the DMA request by putting high on its HDLA (hold acknowledge), thus telling the 8237 DMA that it can go ahead and use the bus performs its task. HOLD must remain active high as long as DMA performing task.
DMA will activate DACK (DMA acknowledge), which tell the peripheral device that it will start to transfer the data.
DMA starts to transfer the data from memory to peripheral by putting the address of the first byte of the block on the address bus and activating MEMR, thereby reading the byte from memory into the data bus; it then activate IOW to write it to the peripheral. The DMA decrements the counter and increments the address pointer and repeats this process until the count reaches and task is finished.
After the DMA has finished its job, it will deactivate HRQ, signaling the CU that it can regain control over its buses.
4.6 Chapter Review Questions
Which of the following are I/O techniques?
Ans: A and C
Which the following line is used to identify location of I/O device?
Which of the following components are included in I/O device interface?
Ans: B and C
The system bus consists of _______________.
Ans: A, B and C
Which of the following is not function of I/O module?
Providing time and control signals
Communicating with CPU
Communication with I/O devices
None of these
The peripheral device will request for the service, which generated______ signal.
None of these
Intel 8237A DMA Controller consists of ______ I/O channels.
Which of the following DMA mode stops CPU from accessing system bus?
Block Transfer Mode
None of these
Intel 8237A DMA Controller consists of ____ number of registers?
10. MMU stands for ——————–
Memory Mixture unit
Memory Management Unit
Memory measurement Unit
None of these
2. A and C
In the chapter, I/O Organisation, you learnt about:
I/O modules and its function.
I/O module structure.
Different types of I/O techniques.
Intel 8237A DMA Controller..
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