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FPGA Architectures and Implementing a Counter for Terasic Altera DE0 FPGA Board

Paper Type: Free Essay Subject: Information Technology
Wordcount: 3825 words Published: 23rd Sep 2019

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Table of Contents

Table of Figures

List of Tables

1 Introduction – FPGA Architectures

1.1 What is FPGA?

1.2 Why FPGA?

1.3 Stakeholders

2 Issues with the current approach

2.1.1 The FPGA Standoff

2.1.2 Why FPGA Over Other Chips?

3 Aim and Objectives

3.1 Objectives

3.2 Research Questions

3.3 Added Value and MOV

4 Approach for the Research Paper

4.1 Development Methodology

4.1.1 Design Entry

4.1.2 Functional Simulation

4.1.3 Analysis & Synthesis

4.1.4 Place & Routes

4.1.5 Simulation & Synchronization

4.1.6 Programming and Configuration

4.1.7 Download to Chip

4.2 Deliverables

4.3 Resources Required

4.4 Project Risks

5 Team & Planning

5.1 Gantt Chart


Table of Figures

Figure 1: Diagrammatic representation of an average FPGA board

Figure 2: Representation of gates in FGPA and CPU

Figure 3: Altera FPGA design flow

Figure 4: Gantt Chart representation for all the scheduled tasks

List of Tables

Table 1: Comparative analysis between FGPA, CPU, GPU, DSP processing


1         Introduction – FPGA Architectures

The aim of our research is to explore Field Programmable Gate Array (FPGA) by performing a systematic review of FPGA architectures and preparing a how to guide document for implementing a counter on Terasic DE0 FPGA board which uses Altera Cyclone III chip.

The research will have three parts to it.

      Systematic review of FPGA architectures

      Implementation of a counter on Terasic DE0 FPGA board

      How to guide document of implementing a counter on Terasic DE0 FPGA board which use Altera Cyclone III chip

Systematic review will be focused on available FPGA architectures by reviewing previous literature and by analyzing different FPGA architectures developed by different vendors in the market.

Part two will be oriented more towards the practical aspect of the research. We will develop a counter using Verilog Hardware Description Language and implement it on the FPGA chip by configuring and downloading it to DEO board.

Based on the practical performed in part two we will implement the counter on the Terrasic DEO FPGA board. Finally, we will document how we did it so that it will be beneficial for the future students to understand the complexities we faced and how we overcame them. Also, it will become basis for the further research that our successors will perform.

To understand the scope and the aim of the project, it is important to first understand some fundamentals of FPGA. Following are some important questions that you should know about FPGA.

1.1         What is FPGA?

FPGA stands for Field Programmable Gate Array. In layman language, it can be configured or reconfigured after it is manufactured by the end user or the manufacture itself. Technically, the manufactured board has the elements embedded in it but they are not wired. The end user can use design software to program the gates to make the board function in a particular way.

Figure 1: Diagrammatic representation of an average FPGA board

1.2         Why FPGA?

The importance of FPGA stems from the very basic concepts of reuse, reduce and fast. To understand this, we will have to understand not many companies have enough resources to research and develop low level hardware like CPUs. To epitomize, intel has to spend billions of dollars, months of time and other resources to fix any hardware bugs. With the implementation of FGPA architecture, it can minimize this loss of resources (reduce) and then the end user can reuse the hardware for multiple applications as it can be reprogrammed for every use.

Furthermore, FPGAs are fast. It is because they have multiple inputs and outputs available and it can be programmed so that it can take multiple inputs, quickly process it and give simultaneous outputs. Which cannot be the case with the ordinary hardware.

Nevertheless, there are many other adverse effects with current approach of manufacturing hardware which can be reduced by switching to FPGA as they promote reusability and reducibility. One of them is the environmental impact that is caused due to the manufacturing and dismantling process of such hardware as they are not environment friendly and cannot be easily disposed and end up in landfills.

Table 1: Comparative analysis between FGPA, CPU, GPU, DSP processing

1.3         Stakeholders

This research paper on Field Programmable Gate Array, FPGA has the following entities as the stakeholders.

  • Dr. Firas Al-Ali and Dr. Fadi Fayez
  • Manukau Institute of Technology
  • FPAG Starters
  • Industries in alliance with FPGA

2         Issues with the current approach

FPGA as a technology is more prevalent than a normal eyes notices around it. If you try to find out, you will be amazed to know it is implemented in the various sectors which we tend to use every day. It is used in the cell phone towers to do signal integrity, decoding and sending Ethernet packages. It is used in defense and military systems. It is used in the medical industry in machines like MRI. All this point in one direction, FPGA is used in the application that requires high processing power and is fast. It is safe to say that the current approach is headed towards the right direction where FPGA will be more prevalent and will replace the technology that we use today. We have established that various industries are using FPGA but that is just a small portion of the market there has to be some roadblocks for the technology which needs research and development to evolve and grow.

2.1.1        The FPGA Standoff

FPGA has some deadlocks in the way it has to be implemented. Several companies and individuals are attempting to overcome these. Following are the issues that FPGA currently faces. (Green, 2014) (A. Muthuramalingam, 2008)

  • High Cost
  • Difficult design and implementation
  • Unreliable functioning

High Cost; As the technology is relatively new and not many manufactures are in the market to produce them. The biggest player in this sector is Intel which has recently acquired the company Altera which produces the FPGA boards. (Intel, n.d.) All of this drives the cost of the chip higher as compared to the other boards available in the market.

Difficult design and implementation; All the low-level elements of the board are embedded but not wired in FPGA boards. For the record, just to boot up the device user has to program the device and make sure hundreds of elements are connected perfectly from the hardware side and the software is running in sync. (EEVBlog, 2014)

Unreliable functioning; As there are multiple input outputs in the board, when working with them and running large instances it is hard to debug and fix errors. Moreover, for larger instances often users have to use more than one FPGA boards which makes the problem even harder to solve.

2.1.2        Why FPGA Over Other Chips?

FPGA was first commercially introduced in the mid-80s and were pretty simple and didn’t do much. Today, FPGAs have become very complex with hundreds and thousands of gates in them which can be configured and reprogrammed according to the need. Some of the biggest attractions for FPGA over other boards are as follows. (NandLand, 2015)

  • Fast
  • Reprogrammable
  • High power

Fast; FPGA has high support for I/O which means more pins are available on the board. To epitomize, end user can run multiple cores at once and get it to run multiple instance at once get results simultaneously.

Figure 2: Representation of gates in FGPA and CPU

Reprogrammable; It is one of the most attractive feature of FPGA boards. On an average board, user can use a design suit like ISE or NIOS II to program the gates available on the board to force the board to function according to the need.

High Power; Re-Programmable and Fast characteristic of FPGA makes it very powerful which compensates for its high cost. With reprogramming the board can be set to accelerate the normal processes and overclocking becomes easier and can be done with way more potential.

3         Aim and Objectives


     Develop a How to Guide based on practical implementation of a counter on Terasic DE0 board which use Altera Cyclone III FPGA chip.

     Develop a Systematic Review of FPGA Architectures: Survey, Observations and Future Trends

3.1         Objectives

  • Develop a counter by using Verilog.
  • Implement it on Terasic Development And Education 0 (DE0) board.
  • Prepare a How to Guide document on the practical.
  • Develop a Systematic Review on FPGA architectures.

3.2         Research Questions

      Lack of comparison between different FPGA architectures.

      Difficult for students and starters to get in to FPGA technology.

3.3         Added Value and MOV

Along with the deliverables of the research there is a How to guide which will be a documentation on how we worked and implemented our practical on the supplied FPGA board. This documentation will be of significant value to our successors researching in the same segment.

Secondly, once the research paper and implementations are completed we aim to showcase our work in Information Technology conferences.

4         Approach for the Research Paper

4.1         Development Methodology

A General Altera FPGA design flow for Terasic boards will be used for the practical implementation. This budding technology will not be having abundant support from other resources, so we will need to plan adequately and implement properly. Following is the diagram highlighting the technicalities and the work flows that our approach will be based upon.

Figure 3: Altera FPGA design flow

4.1.1        Design Entry

Both HDL (Hardware Description Language) text entry and Schematic designing by Quartus 11 Schematic Editor will be used for the Design Entry phase. Verilog will be the preferred HDL.

4.1.2        Functional Simulation

Test waveforms will be used as functional simulations for testing the design.

4.1.3        Analysis & Synthesis

Here design source files will be checked for errors, optimized and listed generating a connection list. The process is also called as net listing. Then this netlist is mapped in to the FPGA architecture.

4.1.4        Place & Routes

In this phase logical design will be fitted in to a smallest possible part of the chip by using a “Balanced” approach. Both RTL viewer and chip planner will be used as graphical representations of chip and its logical resources. Quarters 11 fitter will use the database generated in previous phase to place all the logic functions in most suited logic cells in order to provide best routing and timing. Hence the interconnections between cells will be placed and pin assignments will be done accordingly.

4.1.5        Simulation & Synchronization

Timing tools such as TimeQuest timing analyzer will be used for static timing analysis. Issues with clock synchronizing will be addressed. Model Sim will be used for timing simulations and to generate accurate timing diagrams against every signal of the design.

4.1.6        Programming and Configuration

Finally, Quartus 11 Assembler will be used to generate the programming files out of successfully compiled logic design with pin assignments etc.

4.1.7        Download to Chip

A USB Blaster will be used to download the program files to the chip. Quartus 11 Programmer option will be used for this step.

4.2         Deliverables

The project deliverables will be as follows

  1. How to Guide
  2. Implementation of reaction timer program on FPGA Board
  3. Literature Review

4.3         Resources Required

This is more of a theoretical project as it is more research oriented. The only resources we need are the hardware components to implement the practical side of the research which is to implement a reaction timer program on FPGA Board.

      Terasic Altera DE0 Cyclone III FPGA Board

      Quartus II Software suit

      A computer

      Previous documentations and how to guides for other available boards. NOTE – There is no “how to guide” on practical FPGA implementations from the scratch available on the Terasic Altera Cyclone III FPGA Board in MIT.

4.4         Project Risks

After a group self-analysis, we came up with some of the risks that we have which could affect our research. We will discuss them in the following section.

  • Time Crunch
  • Lack of expertise
  • Hardware

Time Crunch; All of our group members our international students working 20 hours and working on at least one more paper alongside with this research for Hot Topic. On the top, all of this is concentrated over eight weeks. Balancing work, education and life is a very challenging task during these eight weeks. If not done perfectly, time will be an obstacle for our team.

Lack of expertise; FPGA is an untouched topic for all the members of our team. Moreover, one of the members is from Software major who never even came close to hardware. We have two Networking major students in the team who are confident and believe that FPGA is easy and can be learnt and implemented according to this proposal. Anyhow, there are hundreds of pages long documentations and blogs that we have to read before we could start any research or do write ups on the topic.

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Hardware; we have selected hardware according to the needs of our project from the range of hardware available from Dr. Firas Al-Ali. Again, we are not experienced to work with any of this hardware. Moreover, the hardware is not equipped with the latest gizmos which makes everyone’s life easy and there is not enough support available online. So, in cases we have to adopt trial and error approach while working with the hardware.

5         Team & Planning

As a team, in our first minute meet we tried and divided responsibilities amongst ourselves. Rakshit Bhaskar was selected as the Team Leader and all the members of the team were allocated tasks.

5.1         Gantt Chart

Based on the team meetings and decisions we have allocated all the tasks a start date, an end date and duration of the tasks. This helped us in our project management and we created a Gantt chart to depict the flow we aim to work during the research in order to achieve our objectives. The tasks are divided in five major segments namely Planning, Designing, Course Work, Testing and Documentation. The following image provides more insights on the categories and tasks allocated under it.


  • Muthuramalingam, S. H. (2008). Neural Network Implementation Using FPGA: Issues and Application. Auckland: International Journal of Electrical and Computer Engineering.
  • Bhaskar, R. (2018). DE0 with Cyclone III FPGA chip. Manukau Institute of Technology, Auckland.
  • EEVBlog (2014). EEVblog #635 – FPGA’s Vs Microcontrollers [Recorded by EEVBlog].
  • Green, R. (2014, 09 19). Five Challenges to FPGA-Based Prototyping. Retrieved from EE Times: https://www.eetimes.com/author.asp?section_id=36&doc_id=1324000
  • Intel. (n.d.). Intel FPGAs and Programmable Devices. Retrieved from Intel: https://www.intel.com/content/www/us/en/products/programmable.html
  • Moore, A., & Wilson, R. (2017). FPGA for Dummies (Vol. 2nd intel edition). (R. Wilson, Ed.) John Wiley & Sons, Inc.
  • Nanayakkra, H. (2018, 10 29). Gantt Chart – FPGA – Hot Topic.
  • NandLand (2015). What is an FPGA? Intro for Beginners [Recorded by NandLand].
  • Stemmer Imaging. (2018). A list of key differences between FPGA, DSP, GPU and CPU. Retrieved from Stemmer Imaging: https://www.stemmer-imaging.co.uk/en/technical-tips/introduction-to-fpga-acceleration/
  • Stemmer Imaging. (n.d.). Introduction to FPGA acceleration. Retrieved from Stemmer Imaging: https://www.stemmer-imaging.co.uk/en/technical-tips/introduction-to-fpga-acceleration/
  • Stephen Brown, J. R. (1996). Architecture of FPGAs and CPLDs. University of Toronto, Department of Electrical and Computer Engineering, Toronto.
  • Taylor, R. (2017, 11 17). FPGAs Supercharge Computational Performance . Retrieved from infoQ: https://www.infoq.com/articles/fpga-computational-performance
  • Xilinx. (2018). Field Programmable Gate Array (FPGA). Retrieved from Xilinx: https://www.xilinx.com/products/silicon-devices/fpga/what-is-an-fpga.html


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